37C3 – Open CPU / SoC design, all the way up to Debian

4 thoughts on “37C3 – Open CPU / SoC design, all the way up to Debian”

• watched it with factor of 1.75 and did not understand much, intellectually. Riscv has potential, Linux is great!

• nice

• at 30:50, man that sounds like Linus Torvalds

• 00:22 🚀 The speaker has a software and electronic engineering background, and the talk focuses on the development of a RISC-V softcore with unique features like out-of-order execution.
  02:16 🧠 Open-source hardware description tools, like those based on Scala or Python, use general-purpose programming languages and software IPs to define hardware, offering alternatives to industry standards.
  05:17 ⚙ RISC-V architecture has a stable toolchain, and various companies embed RISC-V in silicon for specific functionalities, making it a common choice in the industry.
  07:06 🔍 Branch prediction involves predicting the next program counter early in the pipeline, considering factors like branch or jump instructions, their type, and destination.
  09:22 📊 Simulation tools like Konot allow detailed cycle-by-cycle analysis of CPU execution, aiding in understanding and testing vulnerabilities, as demonstrated with a Spectre attack on a RISC-V CPU.
  11:53 🔄 Hardware cache coherence is essential for running RISC-V Linux, and the speaker emphasizes the difference between software and hardware cache coherence, highlighting the performance impact.
  13:55 🕹 Observing memory access patterns and maintaining proper alignment is crucial for optimizing performance in hardware cache coherence, illustrated through a C code example.
  16:21 🛠 Open-source tools like LiteX enable designing full systems-on-chip (SoC) with peripherals, providing templates for customization and deployment on various FPGA development kits.
  17:44 🚥 Implementing USB support in FPGA designs is achievable using open-source specifications like OR1K's USB core, demonstrating cross-platform compatibility.
  19:55 🐧 Running Linux on RISC-V requires specific hardware and features, including machine modes, MMU support, atomic support, and Supervisor Binary Interface (SBI) implementation.
  21:29 📑 Generating Debian images for RISC-V softcores involves meeting certain requirements like RISC-V 64-bit support, specific Linux kernel flags, and storage (SD card).
  22:34 📦 Accessing Debian desktop environments on FPGAs introduces a wide range of software packages, providing a desktop-like experience on embedded hardware.
  23:03 🚗 The speaker shares the emotional roller coaster of debugging complex CPU designs, comparing it to a scene from Breaking Bad.
  24:09 🐛 Debugging challenges are illustrated with an example where a car had to run for 1 hour before encountering a rare bug, highlighting the difficulty in simulation.
  26:20 🛠 Open-source alternatives like Verilator are crucial for simulating CPUs, providing speed advantages over industry-standard tools.
  27:29 ⚙ Running a CPU in lockstep with a reference model during simulation is emphasized as a key practice for catching errors early and maintaining sanity.
  30:28 🌐 The integration of the Debian image with the RISC-V CPU isdiscussed, suggesting that specific Debian ports may not be necessary, simplifying the process.
  31:07 🏎 The feasibility of running a CPU without branch prediction is discussed, acknowledging a performance hit but emphasizing usability, especially with Vex and v5.
  34:59 🏗 The slow simulation on FPGA is explained, clarifying that FPGAs are not primarily simulation devices and noting the age of the specific FPGA used.
  36:13 🔄 Running dual-core CPUs in lockstep is achieved through the development of "lvls," allowing live checking of the CPU or file-based validation.
  37:22 🔄 Different CPU implementations can run in lockstep using multiple frontends, providing flexibility for diverse CPU designs.
  38:17 🕵 The speaker uses GDB and OpenOCD for debugging but doesn't currently employ advanced tools for extracting detailed execution graphs during real tracing.

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