OpenLANE Workshop Day 6: Tapeout Pakistan

Day6: Clock Tree Synthesis (CTS)

This workshop will be conducted by MERL-UIT in collaboration with Open-Source FPGA (OSFPGA) Foundation, it is based on 8 days of outcome-based training, this is the 6th session of the training that will be held on 10th-August-2021 at 06:00 PM PKT, and these sessions are scheduled for 2 days per week. i.e Tuesday and Thursday.

A detailed schedule is given below:
Day1: Introduction to APR, OpenLANE, and Sky130 PDK
Day2: Getting started with OpenLANE and CMOS
Day3: RTL Synthesis & STA
Day4: Floorplan + PDN
Day5: Placement
Day6: Clock Tree Synthesis (CTS)
Day7: Routing
Day8: Final Steps toward GDS

Prerequisite:
1. Join Slack Channel: https://join.slack.com/t/aprtraining/…
2. Watch the previous session: https://www.youtube.com/watch?v=jDPnI…
3. Complete this Verilog training: https://www.youtube.com/watch?v=nblGw…
3.1: Practice on this tool(Icarus Verilog): https://iverilog.fandom.com/wiki/Inst…
4. Install Linux OS as a dual boot: https://youtu.be/u5QyjHIYwTQ
OR install it on Virtual Machine: https://youtu.be/x5MhydijWmc

Other Links:
Website: https://www.merledupk.org
Facebook: https://business.facebook.com/merluit
LinkedIn: https://www.linkedin.com/company/merluit
Instagram: https://www.instagram.com/merluit
Twitter: https://twitter.com/merluit
GitHub: https://github.com/merledu

source

by Micro Electronics Research Lab -UIT

linux foundation